MIT Puts 36-Core Internet on a Chip | EE Times

Today many different interconnection topologies are used for multicore chips. For as few as eight cores direct bus connections can be made — cores taking turns using the same bus. MIT’s 36-core processors, on the other hand, are connected by an on-chip mesh network reminiscent of Intel’s 2007 Teraflop Research Chip — code-named Polaris — […]

Why Microsoft is building programmable chips that specialize in search — Tech News and Analysis

SUMMARY: Microsoft has been experimenting with its own custom chip effort in order to make its data centers more efficient, and these chips aren’t centered around ARM-based cores, but rather FPGAs from Altera. via Why Microsoft is building programmable chips that specialize in search — Tech News and Analysis. FPGAs for the win, at least for […]

Xilinx Introduces SDNet & ‘Softly’ Defined Networks | EE Times

It’s not often that you see something that makes you think “this is a game changer.” The introduction of logic synthesis circa 1990 was one such event; today’s introduction of SDNet from Xilinx may well be another. via Xilinx Introduces SDNet & ‘Softly’ Defined Networks | EE Times. Cisco has used different RISC chips over […]

10 Reasons OpenCL Will Change Your Design Strategy & Market Position | EE Times

OpenCL is a breakthrough precisely because it enables developers to accelerate the real-time execution of their algorithms quickly and easily — particularly those that lend themselves to the considerable parallel processing capabilities of FPGAs (which yield superior compute densities and far better performance/Watt than CPU- and GPU-based solutions) via 10 Reasons OpenCL Will Change Your […]

Maxeler Makes Waves With Dataflow Design – Digits – WSJ

In the dataflow approach, the chip or computer is essentially tailored for a particular program, and works a bit like a factory floor. via Maxeler Makes Waves With Dataflow Design – Digits – WSJ. My supercomputer can beat your supercomputer, and money is no object. FPGAs (Field Programmable Gate Arrays) are used most often in […]