Xilinx Introduces SDNet & ‘Softly’ Defined Networks | EE Times

It’s not often that you see something that makes you think “this is a game changer.” The introduction of logic synthesis circa 1990 was one such event; today’s introduction of SDNet from Xilinx may well be another. via Xilinx Introduces SDNet & ‘Softly’ Defined Networks | EE Times. Cisco has used different RISC chips over […]

Maxeler FPGA Project

Originally posted on Software Trading:
Lately, I’ve been exploring a little known corner of high performance computing (HPC) known as FPGAs. Turns out, it’s time to get electrical on yowass (Pulp Fiction reference intentional). You can program these chips in the field, thus speeding up processing speeds dramatically, relative to generic CPUs. It’s possible to customize functionality…

Maxeler Makes Waves With Dataflow Design – Digits – WSJ

In the dataflow approach, the chip or computer is essentially tailored for a particular program, and works a bit like a factory floor. via Maxeler Makes Waves With Dataflow Design – Digits – WSJ. My supercomputer can beat your supercomputer, and money is no object. FPGAs (Field Programmable Gate Arrays) are used most often in […]

EMC’s all-flash benediction: Turbulence ahead • The Register

All the Fear, Uncertainty and Doubt (FUD) spread by big legacy manufacturers of hard drive storage in the data center is a way to stem or delay the burgeoning tidal wave of Flash memory based storage. Yes the economics of Flash based storage are not quite there yet, but for the high performance, high throughput folks the future is now.

Intel lets outside chip maker into its fabs • The Register

    According to Greg Martin, a spokesman for the FPGA maker, Achronix can compete with Xilinx and Altera because it has, at 1.5GHz in its current Speedster1 line, the fastest such chips on the market. And by moving to Intel’s 22nm technology, the company could have ramped up the clock speed to 3GHz. via […]