As research is being done on incremental improvements in Lithium Ion batteries, some occasional discoveries are being made. In this instance, the anode is being switched to pure lithium with a coating to protect the very reactive metal surface. The problem with using pure lithium is the growth of micro crystalline “dendrites”, kind of like stalagmites/stalactites in caves, along the whole surface. As the the dendrites build up, the anode loses it’s efficiency and that battery slowly loses it’s ability to charge all the way. This research has shown how to coat a pure lithium anode with a later of carbon nanotubes to help act as a permeable layer between the the electrolytic liquid in the battery and the pure lithium anode.
In past articles on Carpetbomberz.com we’ve seen announcements of other possible battery technologies like Zinc-Air, Lithium-Air and possible use of carbon nanotubes as a anode material. This announcement is promising in that it’s added costs might be somewhat smaller versus a wholesale change in battery chemistry. Similarly the article points out how much lighter elemental Lithium is versus the current anode materials (Carbon and Silicon). If the process of coating the anode is sufficiently inexpensive and can be done on a industrial production line, you will see this get adopted. But with most experiments like these, scaling up and lowering costs is the hardest thing to do. Hopefully this is one that will make it into shipping products and see the light of day.
Today many different interconnection topologies are used for multicore chips. For as few as eight cores direct bus connections can be made — cores taking turns using the same bus. MIT’s 36-core processors, on the other hand, are connected by an on-chip mesh network reminiscent of Intel’s 2007 Teraflop Research Chip — code-named Polaris — where direct connections were made to adjacent cores, with data intended for remote cores passed from core-to-core until reaching its destination. For its 50-core Xeon Phi, however, Intel settled instead on using multiple high-speed rings for data, address, and acknowledgement instead of a mesh.
I commented some time back on a similar article on the same topic. It appears now the MIT research group has working silicon of the design. As mentioned in the pull-quote, the Xeon Phi (which has made some news in the Top 500 SuperComputer stories recently) is a massively multicore architecture but uses a different interconnect that Intel designed on their own. These stories as they appear get filed into the category of massively multicore or low power CPU developments. Most times the same CPUs add cores without significantly drawing more power and thus provide a net increase in compute ability. Tilera, Calxeda and yes even SeaMicro were all working along towards those ends. Either through mergers, or cutting of funding each one has seemed to trail off and not succeed at its original goal (massively multicore, low power designs). Also along the way Intel has done everything it can to dull and dent the novelty of the new designs by revising an Atom based or Celeron based CPU to provide much lower power at the scale of maybe 2 cores per CPU.
Like this chip MIT announced Tilera too was originally an MIT research product spun off of the University campus. Its principals were the PI and a research associate if I remember correctly. Now that MIT has the working silicon they’re going to benchmark and test and verify their design. The researchers will release the verilog hardware description of chip for anyone use, research or verify for themselves once they’ve completed their own study. It will be interesting to see how much of an incremental improvement this design provides, and possibly could be the launch of another Tilera style product out of MIT.
We don’t see infrequent blips of CPU architecture releases from Intel, we get a regular, 2-year tick-tock cadence. It’s time for Intel’s NSG to be given the resources necessary to do the same. I long for the day when we don’t just see these SSD releases limited to the enterprise and corporate client segments, but spread across all markets – from mobile to consumer PC client and of course up to the enterprise as well.
Big news in the SSD/Flash memory world at Computex in Taipei, Taiwan. Intel has entered the fray with Samsung and SandForce issuing a fully NVMe compliant set of drives running on PCIe cards. Throughputs are amazing, but the prices are overly competitive. You can enter the market for as low as $600 for a 400GB PCIe card running as an NVMe compliant drive. On Windows Server 2012 R2 and Windows 8.1 you get native support for NVMe drives. This is going to get really interesting. Especially considering all the markets and levels of consumers within the market. On the budget side is the SATA Express interface which is an attempt to factor out some of the slowness inherent in SSDs attached to SATA bus interfaces. Then there’s M.2 which is the smaller form factor PCIe based drive interface being adopted by manufacturers making light and small form factor tablets and laptops. That is a big jump past SATA altogether and also has a speed bump associated with it as it communicates directly with the PCIe bus. Last and most impressive of all is the NVMe devices announced by Intel with yet a further speed bump as it’s addressing multiple data lanes on PCI Express. Some concern trolls in the gaming community are quick to point out the data lanes are being lost to I/O when they already are maxing them out with their 3D graphics boards.
The route forward it seems would be Intel motherboard designs with a PCIe 3 interface with the equivalent data lanes for two full speed 16x graphics cards, but using that extra 16x lane to devote to I/O instead or maybe a 1.5X arrangement with a fully 16X lane and 2 more 8X lanes to handle regular I/O plus a dedicated 8X NVMe interface? It’s going to require some reengineering and BIOS updating no doubt to get all the speed out of all the devices simultaneously. That’s why I would also like to remind readers of the Flash-DIMM phenomenon as well sitting out there on the edges in the high speed, high frequency trading houses in the NYC metro area. We haven’t seen nor heard much since the original product announcement from IBM for the X6-series servers and the options for Flash-DIMMs on that product line. Smart Memory Technology (the prime designer/manufacturer of Flash-DIMMs for SanDisk) has now been bought out by SanDisk. Again now word on that product line now. Same is true for the Lenovo takeover of IBM’s Intel server product line (of which the X6-series is the jewel in the crown). Mergers and acquisitions have veiled and blunted some of these revolutionary product announcements, but I hope eventually that Flash-DIMMs see the light of day and gain full BIOS support and eventually make it into the Desktop computer market. As good as NVMe is going forward, I think we need too a mix of Flash-DIMM to see the full speed of the multi-core X86 Intel chips.
As I’ve had to deal with using webcams stretched across very long distances in classrooms and lecture halls, a 30 meter cable can be a godsend. I’ve used 10 meter long cables with built-in extenders and even that was a big step up. Here’s hoping prices eventually come down to a reasonable price level, say below $100. I’m impressed the power can run across the same cable with the optical fiber. I assume both ends are electrical-optical converters, meaning they need to be powered. So compared to CAT-5 cables with extenders it seems pretty light weight. No need for outlets to power the extenders on both ends.
Of course CAT-5 based extenders are still very price competitive and come in so many formats, USB 3.0 is trivial and probably more price competitive in the 30 meter range. But cable runs in CAT5 can be 50 to 100 meters for data running over TCP/IP on network switches. So CAT-5 with extenders converting to USB will still have the cost and performance advantage for some time to come.
First a little background info on what is a capacitor: https://en.wikipedia.org/wiki/Ultracapacitor#History
In short it’s like a very powerful, high density battery for smoothing out the “load” of an electrical circuit. It helps prevent spikes and dips in the electricity as it flows through a device. But with recent work done on ultra-capacitors they can be more like a full-fledged battery that doesn’t ever lose it’s charge over time. When they are combined up with a real live battery you can do some pretty interesting things to both the capacitor and the battery to help them work together, allowing longer battery life, higher total amount of charge capacity. Many things can flow from combining ultracapacitors with a really high end Lithium ion battery.
Any technology, tweak or improvement that promises at minimum 10% improvement over current Lithium ion battery designs is worth a look. They’re claiming a full 15% in this story from The Reg. And due to the re-design it would seem it needs to meet regulatory/safety approval as well. Having seen the JAL Airlines suffer battery issues on the Boeing 787, I couldn’t agree more.
There will be some heavy lifting needing to be done between now and when a product like this hits the market. Testing and failure analysis will ultimately decide whether or not this ultra-capacitor/Lithium ion hybrid is safe enough to use for consumer electronics. I’m also hoping Apple and other manufacturer/design outfits like Apple are putting some eyes, ears and phone calls on this to learn more. Samsung too might be interested in this, but are seemingly more reliant for battery designs outside of their company. That’s where Apple has the upperhand long term, they will design every part if needed in order to keep ahead of the competition.
The researchers harvested single sheets of tungsten selenide (WSe2) using adhesive tape, a technique invented for the production of graphene. They used a support and dielectric layer of boron nitride on a base of silicon dioxide on silicon, to come up with the thinnest possible LED.
Wow, it seems like the current research in graphene has spawned at least one other possible application, using adhesive tape to create thin layers of homogeneous materials. This time it’s a liquid crystal material with possible applications in thin/flexible LCD displays. As the article says until now Organic LED (OLED) has been the material of choice for thin and even flexible displays. It’s also reassuring MIT was able to publish some similar work in the same edition of Nature magazine. Hopefully this will spur some other researchers to put some money and people on pushing this further.
With all early announcements like this in a fully vetted, edited science journal, we won’t see the products derived from this new technology very soon. However, hope spring eternal for me, and I know just like with OLED, eventually if this can be further researched and it’s found to be superior in cost/performance, it will compete in the market place. I will say the steps in fabrication the researchers used are pretty novel and show some amount of creativity to quickly produce a workable thin film without inordinately expensive fabrication equipment. I thinking about specifically the epitaxial electron beam devices folks have used for nano-material research. Like a 3D printer for atoms these devices are a must-have for many electronics engineering and materials researchers. And they are notoriously slow (just like 3D printers) and expensive for each finished job (also similar to 3D printers). The graphene approach to manufacturing devices for research started with making strands of graphite filaments by firing a laser at a highly purified block of carbon, until after so many shots, eventually you might get a shard of a graphene sheet showing up. Using adhesive tape to “shear” a very pure layer of graphite into a graphene sheet, that was the lightning bolt. Simple adhesive tape could get a sufficiently homogeneous and workable layer of graphene to do real work. I feel like there’s a similar approach or affinity at work here for the researchers who used the same technique to make their tungsten selenide thin films for their thin LED displays.
Imagine being able to immerse yourself in another world, without the limitations of a TV or movie screen. Virtual reality has been a dream for years, but judging by current trends, it may not be just a dream for much longer.
I won’t claim that when a technology gets written up in Consumer Reports it has “jumped the shark”, no. Instead I would rather give Consumer Reports kudos for keeping tabs on others writing up and lauding the Oculus Rift VR headset. The specifications of this device continue to improve even before it is hitting the market. Hopes are still high for the prices to be reasonable (really it needs to cost no more than a bottom of the line iPad if there’s any hope of it taking off). Whether the price meets everyone’s expectations is very dependent on the sources for the materials going into the headset, and the single most expensive item are the displays.
OLED (Organic LED) has been used in mobile phones to great effect, the displays use less power and have somewhat brighter color than backlit LCD panels. But they cost more, and the bigger the display the higher the cost. The developers of Oculus Rift have now pressed the cost maybe a little higher by choosing to go with a very high refresh rate and low latency for the OLED screens in the headset. This came after first wave of user feedback indicating too much lag and subsequent headaches due to the screen not keeping up with head movements (this is a classical downfall of most VR headsets no matter the display technology). However Oculus Rift has continued to work on the lag in the current generation head set and by all accounts it’s nearly ready for public consumption. It’s true, they might have fixed the lag issue and most beta testers to date are complimenting the changes in the hardware. This might be the device that launches a thousand 3D headsets.
As 3D goes, the market and appeal may be very limited, that historically has been the case. Whether it was used in academia for data visualization or in the military for simulation, 3D Virtual Reality was an expensive niche catering to people with lots of money to spend. Because Oculus Rift was targeted at a lower price range, but with fantastic performance visually speaking who knows what market may follow it’s actual release. So as everyone is whipped up into a frenzy over the final release of the Oculus Rift VR Headset, keep an eye out for this. It’s going to be hot item in limited supply for a while I would bet. And yes, I do think I would love to try one out myself, not just for gaming purposes but for any of the as yet unseen applications it might have (like the next Windows OS or Mac OS?)
“The eXFlash DIMM is an option for IBM‘s System x3850 and x3950 X6 servers providing up to 12.8 TB of flash capacity. (Although just as this story was being written, IBM announced it was selling its x86 server business to Lenovo for $2.3 billion).”
Sadly it seems the party is over before it even got started in the sales and shipping of UltraDIMM equipped IBM x86 servers. If Lenovo snatches up this product line, I’m sure all the customers will still be perfectly happy but I worry about that level of innovation and product testing that led to the introduction of UltraDIMM may be slowed.
I’m not criticizing Lenovo for this, they have done a fine job taking over the laptops and desktop brand from IBM. The motivation to keep on creating new, early samples of very risky and untried technologies seems to be more IBM’s interest in maintaining it’s technological lead in the data center. I don’t know how Lenovo figures into that equation. How much will Lenovo sell in the way of rackmount servers like the X6 line? And just recently there’s been rumblings that IBM wants to sell off it’s long history of doing semi-conductor manufacturing as well.
It’s almost too much to think R&D would be given up by IBM in semi-conductors. Outside of Bell Labs, IBM’s fundamental work in this field brought things like silicon on insulator, copper interconnects and myriad other firsts to ever smaller, finer design rules. While Intel followed it’s own process R&D agenda, IBM went its own way too always trying to find advantage it’s in inventions. Albeit that blistering pace of patent filings means they will likely never see all the benefits of that Research and Development. At best IBM can only hope to enforce it’s patents in a Nathan Myhrvold like way, filing law suits on all infringers, protecting it’s intellectual property. That’s going to be a sad day for all of us who marveled at what they demoed, prototyped and manufactured. So long IBM, hello IBM Global Services.
Like the native API libraries, directFS is implemented directly on ioMemory, significantly reducing latency by entirely bypassing operating system buffer caches, file system and kernel block I/O layers. Fusion-io directFS will be released as a practical working example of an application running natively on flash to help developers explore the use of Fusion-io APIs.
Another interesting announcement from the folks at Fusion-io regarding their brand of PCIe SSD cards. There was a proof of concept project covered previously by Chris Mellor in which Fusion-io attempted to top out at 1 Billion IOPs using a novel architecture where PCIe SSD drives were not treated as storage. In fact the Fusion-io was turned into a memory tier bypassing most of the OSes own buffers and queues for handling a traditional Filesystem. Doing this reaped many benefits in terms of depleting the latency inherent with a FileSystem and how it has to communicate through the OS kernel through to the memory subsystem and back again.
Considering also work done within the last 4 years or more using so-called “in memory’ databases and big data projects in general a product like directFS might pair nicely with them. The limit with in memory databases is always the amount of RAM available and total number of cpu nodes managing those memory subsystems. Tack on the necessary storage to load and snapshot the database over time and you have a very traditional looking database server. However, if you supplement that traditional looking architecture with a tier of storage like the directFS the SAN network becomes a 3rd tier of storage, almost like a tape backup device. Sounds interesting the more I daydream about it.
And with clock speeds topped out and electricity use and cooling being the big limiting issue, Scott says that an exaflops machine running at a very modest 1GHz will require one billion-way parallelism, and parallelism in all subsystems to keep those threads humming.
Interesting write-up of a blog entry from nVidia‘s chief of super-computing, including his thoughts regarding scaling up to an exascale supercomputer. I’m surprised at how power efficient a GPU is for floating point operations. I’m amazed at these company’s ability to measure the power consumption down to the single operation level. Microjoules and picojoules are worlds apart from on another and here’s the illustration:
1 Microjoule is 1 millionth of a joule or 1×10-6 (six decimal places) whereas 1 picojoule is 1×10-12 or twice as many decimal places a total of 12 zeroes. So that is a HUGE difference 6 orders of magnitude in efficiency from an electrical consumption standpoint. The nVidia guy, author Steve estimates that to get to exascale supercomputers any hybrid CPU/GPU machine would need GPUs that have one order of magnitude higher efficiency in joules per floating point operation (FLOP) or 1×10-13, one whole decimal point better. To borrow a cliche, Supercomputer manufacturers have their work cut out for them. The way forward is efficiency and the GPU has the edge per operation, and all they need do is increase the efficiency that one decimal point to get them closer to the exascale league of super-computing.
Why is exascale important to the scientific community at large? In one segment there’s never enough cycles per second to satisfy the scale of the computations being done. Models of systems can be created but the simulations they provide may not have enough fine grained ‘detail’. The detail say for weather model simulating a period of time in the future needs to know the current conditions then it can start the calculation. But the ‘resolution’ or fine-grained detail of ‘conditions’ is what limits the accuracy over time. Especially when small errors get amplified by each successive cycle of calculating. One way to help limit the damage by these small errors is to increase the resolution or the land area over which you are assign a ‘current condition’. So instead of 10 miles of resolution (meaning each block on the face of the planet is 10miles square), you switch to 1mile resolution. Any error in a one mile square patch is less likely to cause huge errors in the future weather prediction. But now you have to calculate 10x the number of squares as compared to the previous best model which you set at 10miles of resolution. That’s probably the easiest way to see how demands on the computer increase as people increase the resolution of their weather prediction models. But it’s not limited just to weather. It could be used to simulate a nuclear weapon aging over time. Or it could be used to decrypt foreign messages intercepted by NSA satellites. The speed of the computer would allow more brute force attempts ad decrypting any message they capture.
In spite of all the gains to be had with an exascale computer, you still have to program the bloody thing to work with your simulation. And that’s really the gist of this article, no free lunch in High Performance Computing. The level of knowledge of the hardware required to get anything like the maximum theoretical speed is a lot higher than one would think. There’s no magic bullet or ‘re-compile’ button that’s going to get your old software running smoothly on the exascale computer. More likely you and a team of the smartest scientists are going to work for years to tailor your simulation to the hardware you want to run it on. And therein lies the rub, the hardware alone isn’t going to get you the extra performance.